1. Field of the Invention
An aspect of the present invention relates to a nonvolatile semiconductor memory device.
2. Description of the Related Art
For the ferroelectric random access memory, a 1T1C (1 transistor and 1 capacitor) type memory cell is proposed as it is suitable for increasing memory capacity.
The 1T1C type memory cell stores 1-bit data using one transistor and one capacitor, and a data readout is performed by comparing a readout voltage of a memory cell with a reference voltage.
The readout voltage of a memory cell is readout to a bitline, while the reference voltage is readout to a complementary bitline paired therewith. Then, the readout voltage and the reference voltage are compared by amplifying the difference therebetween using a sense amplifier.
In order to generate the reference voltage, a dummy cell including a selection transistor and a dummy capacitor is provided independently from an ordinary memory cell provided for storing data.
It is pointed out that a voltage applied between both electrodes of the dummy capacitor needs setting so as to have not only positive dependence on a temperature but also dependence on an array voltage VAA that is an internal voltage obtained by lowering a power-supply voltage in a chip and that is an operating voltage of the sense amplifier (see, e.g., JP-2007-280458-A).
In JP-2007-280458-A, a reference voltage generation circuit having both the temperature dependence and the array-voltage dependence includes a first current generation circuit configured to generate a first current having an intensity that is constant regardless of a power-supply voltage when temperature is constant and that varies according to change in temperature when temperature changes, a second current generation circuit configured to generate a second current depending on the power-supply voltage, and an output circuit configured to have a resistive element for applying a third current generated by adding the first current and the second current and to output an output voltage generated due to a voltage drop of the resistive element.
In the reference voltage generation circuit, dependence on the array voltage VAA and dependence on temperature T are controlled independently from each other so as to maintain a voltage applied between both electrodes of a dummy capacitor always at an appropriate value to thereby increase a sense margin.
However, in the reference voltage generation circuit of JP-2007-280458-A, the circuit is complicated, and that it is troublesome to adjust the temperature dependence of the voltage to be applied to the dummy capacitor to the temperature dependence of a ferroelectric capacitor.
In addition, in the reference voltage generation circuit of JP-2007-280458-A, if temperature unevenness is caused in a semiconductor chip and if a place where the reference voltage generation circuit is disposed and a place where the dummy capacitor is disposed are spaced from each other, a deviation of the voltage to be applied to the dummy capacitor from an appropriate value and a decrease in the sense margin may occur.